CompuLab Trim-Slice Manuale Utente Scaricare il pdf (Pagina 10)

Interfaces and Connectors

Revised July 2011 Trim-Slice 10

3.2 System Memory

3.2.1 DRAM

The Trim-Slice features 1 GB of DDR2. The DRAM interface is 32-bits wide and runs with a 333

MHz clock.

3.2.2 SPI Flash

The Trim-Slice features 1 MB of SPI NOR flash.

The SPI NOR flash functions as the primary bootable memory device, used for the boot-loader and

configuration blocks storage.

The NOR flash is interfaced with the Tegra2 SoC SPI-SFLASH port.

3.3 Display Subsystem

3.3.1 HDMI

The Trim-Slice HDMI output is implemented with the Tegra2 HDMI interface. HDMI DDC is

implemented with the Tegra2 I2C-1 interface. HDMI_DETECT signal is connected to the Tegra2

HDMI_INT input. HDMI signals are routed to the primary display output connector J1. The HDMI

output supports resolutions of up to 1920 x 1080.

3.3.2 DVI

The Trim-Slice features a DVI transmitter that is based on the TFP410/SIL164 IC. DVI output signals

are routed to the secondary display output connector J2. The DVI transmitter is connected to the

Tegra2 24-bit parallel RGB interface. The DVI output supports resolutions of up to 1680 x 1050.

The DVI DDC is implemented with the Tegra2 I2C-0 interface.

In order to use the DVI interface, the Tegra2 display system has to be configured properly for

RGB888 operation mode.

NOTE: DVI functionality is optional. Availability depends on Trim-Slice model configuration.

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CompuLab Trim-Slice Manuale Utente Pagina 10